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Revision history for Perl extension Verilog::Language.

The contributors that suggested a given feature are shown in [].  [by ...]
indicates the contributor was also the author of the fix; Thanks!

* Verilog::Language 3.013 2007/10/18

****	Fix parsing module #(parameter x,y) declarations. [Oleg Rodionov]

****	Fix parsing system functions with empty parens. [Oleg Rodionov]

****	Fix Verilog::Netlist errors having wrong line number. [Oleg Rodionov]

* Verilog::Language 3.012 2007/09/10

**	Added Verilog::EditFiles module and vsplitmodule example.

* Verilog::Language 3.011 2007/07/31

***	Added event trigger -> operator. [Mark Nodine]

****	Remove preprocessor adding newlines before `line. [Mark Nodine]

* Verilog::Language 3.010 2007/07/18

***	Added Parser::endparse callback. [Mark Nodine]

***	Added SigParser::endmodule, endtaskfunc, and endcell callbacks.

****	Fix attachment of comments to proceeding cells. [David Chinnery]

* Verilog::Language 3.002 2007/07/16

***	Find functions now search backslash escaped names.  [David Chinnery]

***	Fix vrename breakage in 3.00* releases.  [David Price]

****	Fix SigParser::comment to call Parser::Comment. [Mark Nodine]

****	Fix Parser::unreadback to always return value. [Mark Nodine]

****	Fix g++ bug giving "out of memory" on Cygwin.  [Pongstorn]

* Verilog::Language 3.001 2007/06/20

****	Support V2K function/task argument lists.

****	Fix Preprocessor dropping some `line directives.  [Mark Nodine]

****	Fix Netlist "not found" errors on primitives, bug27624. [Jeff Trull]

* Verilog::Language 3.000 2007/06/12

** 	Note this is a MAJOR release that may have incompatibilities with
	earlier versions, although I've attempted to minimize problems.
	Please email any problems to the author.

**	Verilog::SigParser has been completely rewritten.  The good news is
	it understands almost the entire Verilog 2005 language.  The bad
	news is there are minor incompatibilities with previous versions,
	and the parser now errors out when it does not understand something
	rather then ignoring it.

***	The Verilog::SigParser->pin callback now passes "" as the pin name
	instead of "pin###" if connecting by position instead of by name.

***	Added Verilog::SigParser->funcsignal callback for variables declared
	inside a function or task.  bug26972.  [Mark Nodine]
	
***	Added Verilog::SigParser->instant callbacks for gate primitives.
	bug26969, bug27062. [Mark Nodine]
	
***	Added Verilog::SigParser->parampin callbacks for parameter connections
	to instantiations.
	
***	Added Verilog::SigParser->signal_decl callbacks for all module vars,
	including parameters and genvars.
	
***	Added Verilog::SigParser->signal_decl callback argument with 
	initial values of parameters and wires. [Mark Nodine]
	
**	Verilog::Parser has been replaced with the front end of the
	SigParser.  The preproc and syscall callbacks were added

***	Require call to Verilog::Parser->eof() at the end of all parsers.
	
***	Changed Verilog::Parser->unreadback() method to not clear state.
	You must now call unreadback('') to clear the unreadback characters.

***	The long depreciated Verilog::Parse module has been removed.

****	Fixed Verilog::Parser mis-parsing spaces in numbers, bug27070.

****	Fixed Verilog::SigParser bug26141, bug26940, bug26968, bug26969,
	bug26970, bug26972, bug26997, bug27009, bug27010, bug27013,
	bug27036, bug27037, bug27039, bug27045, bug27062, bug27066,
	bug27067, bug27072.  [Mark Nodine, et al]

* Verilog::Language 2.380 2007/05/27

***	Added new Verilog-Perl.pod documentation overview.

***	Verilog::Parser and Verilog::SigParser objects must call the eof method
	to insure forward compatibility.

***	Vpm $info etc have been removed, now only $uinfo, etc are supported.
	This avoids conflict with SystemVerilog $error function.  [Tad Truex]

***	Verilog::Language keywords now uses the `begin_keywords standard names.

***	Added Verilog::Language::number_bitvector and number_bigint for returning
	Bit::Vector and Math::BigInt objects.  bug26967.  [Mark Nodine]

****	Fix --help to use Pod::Usage instead of depreciated pod2text.

****	Ignore quotes inside `protected/`endprotected blocks.

****	Drop end-of-file ctrl-Z's when preprocessing input.

* Verilog::Language 2.373 2007/04/02

***     Fix vppp breaking with Getopt::Long 2.36.  [Andreas J. König]

****	Fix modules without any ports causing lost declarations.  [Mark Nodine]

* Verilog::Language 2.372 2007/02/28

***	Add include_open_nonfatal option to Preproc and Netlist.  [Eric Miller]

****	Fix bug24552; Verilog::Module::new_net now defaults net type
	to 'wire'. [Takeo Komiyama]

* Verilog::Language 2.371 2007/01/23

***	Fix bug24345; supply statements cause lint warnings.  [Jeff Trull]

* Verilog::Language 2.370 2007/01/10

***	Fix bug24248; reg/tri/supply* declarations, etc are now stored in Net
	structures as the declared type, instead of as 'wire'.  [Jeff Trull]

***	Fix bug13462; parse {} concatenations in pin connections. [Jeff Trull]

***	Remove backslashes in quoted symbols when they aren't needed.

****	Fix vpm deleting output when file moved between directories.

* Verilog::Language 2.361 2006/10/02

**	Attach Verilog comments to Netlist objects.  [Monte Becker]

***	Add parameters to Verilog::Parser instant callback.  [Monte Becker]

* Verilog::Language 2.360 2006/09/14

***	Added Preproc keep_whitespace=>0 option to delete whitespace.

***	Preprocessor now strips all DOS carrage returns.

***	Allow Verilog::Getopt::file_path to resolve module_dir and/or incdirs.
	Use only module_dir to resolve Netlist modules.  [by John Tseng]

****    Vrename --crypt now uses lower case random identifiers for readability.

****	Fix DOS carrage returns in multiline defines.  [Ralf Karge]

* Verilog::Language 2.352 2006/08/22

***	Fix compile errors under Cygwin.  [Mattan Tsachi]

* Verilog::Language 2.351 2006/06/08

***     Add vhier --language option.  [Sean Nazareth]

****	Fix Getopt::file_path when dir names match file names. [by John Tseng]

* Verilog::Language 2.350 2006/05/19

***	Vpm now emits $timeformat when passed the --timeformat-units switch.

***	SigParser and the Netlister now ignore function and task IOs.

****	Preproc line numbers being off due to multi-line defines.  [Mat Zeno]

****	Fix `include `DEFINE.

* Verilog::Language 2.341 2006/02/06

***	Add SystemVerilog `0, `1, `x, `z.  [John Tseng]

****	Fix module #() parameter declarations.  [Andy Kuo]

****	Fix "output reg" and "output wire" declarations.  [Andy Kuo]

* Verilog::Language 2.340 2006/01/16

***     Added vpm --minimum switch.

****	Added Verilog::Language::language_standard to allow setting
	which language standard (1995,2001,SystemVerilog) is used for keywords.

****	Fix vhier -o option. [Sean Nazareth]

****	Add vhier --modules and --missing-modules options. [Sean Nazareth]

* Verilog::Language 2.331 2005/10/05

***     Added vhier example program. [Vasu Arasanipalai]

* Verilog::Language 2.330 2005/09/06

***	vpm now aliases $error to $uerror, etc, to avoid conflict
	with SystemVerilog $error function.  [Tad Truex]

***	$uassert_info now uses __message_on. [Vasu Arasanipalai]

****	Fix preprocessor substitution of quoted parametrized defines.

* Verilog::Language 2.321 2005/08/03

***	Verilog::SigParser now sees cells inside generates.  [by Thomas Ziller]

* Verilog::Language 2.320 2005/07/27

***     Add vrename --cryptall option.

***     Fix Language is_keywords to match V2K language spec. [Mark Grossman]
	Deleted extern, makefile, supply.  Added ifnone, strength, unsigned.

****	Fix core dump when missing newline in `define.  [David van der bokke]

* Verilog::Language 2.316 2005/06/10

****	Fix define substitution with incomplete defines.  [by Ronald Dean Smith]

****	Fix C++ Comments causing Perl compile problems. [Merijn Brand]

* Verilog::Language 2.315 2005/03/16

****	Support for latest SystemC::Netlist version.

* Verilog::Language 2.314 2005/03/14

****	Support for latest SystemC::Netlist version.

* Verilog::Language 2.313 2005/03/01

***	Vrename no longer recurses into CVS or .svn directories.

***	Add specparam keyword. [Mark Grossman]

****	Add NC-Verilog, and Verilog::Parser tests.

* Verilog::Language 2.312 2005/02/04

***	Fix ignoring lines with same line number as end of last include.

* Verilog::Language 2.311 2005/01/27

***	Support parsing of signed numbers.  [Rudi Rughoonundon]

**** 	Fix resolve_filename misfinding directories. [John Tseng]

****    Fix Verilog::Getopt::get_parameters for NC-Verilog.

* Verilog::Language 2.310 2005/01/24

**	NEWS is now renamed Changes, to support CPAN indexing. [Offer Kaye]

**	Support Verilog 2001 ansi-style port declarations. [Rudi Rughoonundon]

**	Pins, nets, ports, and cells accessor methods now return lists
	rather then internal hash references.  This matches earlier
	documentation, and behavior of the pins_sorted, etc functions.

***	SigParser::module callback no longer gets list of ports, instead
	SigParser::port is called back on each port.

***	Add Verilog::GetOpt GCC -U<define> switch for undefining.

****	Support SUSE Linux and OS-X. [Jose Renau] 

* Verilog::Language 2.303 2004/11/18

***	Add vpm --nopli for stripping $pli calls. [Mike Lopresti]

* Verilog::Language 2.302 2004/11/10

****	Support Verilog 2001 named instantiation parameters. [Thomas Ziller]

* Verilog::Language 2.301 2004/10/26

****	Fix pod documentation errors. [Offer Kaye]

* Verilog::Language 2.300 2004/04/01

**	Added vppp preprocessor command.

**	Preprocessor is now Verilog 2001 and SystemVerilog 3.1 compliant.
	Adds arguments to defines, and `include <> syntax.

**	Added SystemVerilog 3.1 keywords to Verilog::Language

**	Added vrename --keywords and recursion on directory arguments.

***	Added to SigParser::module callback "$in_celldefine" 4th argument.
	Netlist::File sets $module->is_libcell() either if the file is a
	library or the module is within "`celldefine ... `endcelldefine".

***	Added to Verilog::Netlist (metacomment=>{ firstWord=>val, ... })
	argument.  For each comment that begins with at least two words,
	Verilog::SigParser calls back attribute() if the first word has a
	true value in %metacomment.

***	Module::attrs_sorted() now returns a list of "category name[ =]..."
	strings from metacomments between "module" and the first declaration.

****	(Verilog::Preproc receives the list of metacomment keywords but
	does not yet filter the comments for speed.)

****	Fixed ` substitution inside define value strings.

* Verilog::Language 2.232 3/10/2004

***	Fix newline insertion in vpm $info messages.

* Verilog::Language 2.231 1/27/2004

****	Documentation fixes.

* Verilog::Language 2.230 10/02/2003

**	Vpm has been changed to use Verilog standard flags.
	Vpm will no longer recurse all directories, instead it now accepts
	+incdir+, -v or -f flags as would a regular simulator, and
	preprocesses all files found.

**	Added Netlist::verilog_text for writing netlists. [Phillip Prentice]

***	Added Cell/Port/Pin::delete methods for editing netlists.

***	Added Netlist::top_modules_sorted method.

***	In Netlist, read in library files if cell not found. [John Potter]

***	Fix SigParser dropping 1'b0/1'b1 pins. [John Potter]

***	In vpm, support $error({"concatenate ","string"}); [Ray Strouble]

****	In vpm, fix comments and line numbering in asserts. [Ray Strouble]

****	Fix detection of wire assignments. [David Duxstad]

* Verilog::Language 2.226 8/19/2003

****	GCC 3.3 fixes

* Verilog::Language 2.225 8/12/2003

***	Have Getopt::parameter return unknown arguments from
	inside -f files.  [David Duxstad]

***	Change assert_amone/onehot to use faster equation
	in place of case statement. [Greg Waters]

****	Add tri/tri0/tri1 as wire declarative terms. [David Duxstad]

****	Redhat 9 and GCC 3.2.2 fixes

* Verilog::Language 2.224 5/20/2003

**	Add order based pin/cell connections.  [by David Duxstad]

* Verilog::Language 2.222 3/6/2003

****	Support instantiations with multiple cell names. [Bruce Nepple]

****	Support uppercase radix letters.  [Wilson Li]

* Verilog::Language 2.221 3/4/2003

****	Fix missing example.cpp file

* Verilog::Language 2.220 2/6/2003

***	Support primitives as if they were modules.  [Bruce Nepple]

***	The link_read_nonfatal=>1 netlist option will prevent missing
	modules from being errors during link.  [Bruce Nepple]

***	Add Verilog::Parser support for `protected. [Scott Bleiweiss]

****	Update documentation & Netlist example.  [Bruce Nepple]

* Verilog::Language 2.220 12/27/2002

****	Solaris perl 5.005_03 LD error fixed.  [Mark Moe]
	Solaris note about FILE_OFFSET_BITS.  [Simon Curry]

****	GCC 3.2 use std compile errors fixed. [Eugene Weber]

* Verilog::Language 2.214 10/21/2002

***	Pickup input msb & lsb's.  [Joel Earl]

****	Fix inclusion of x's in $assert_onehot for verilator. [Ray Strouble]

* Verilog::Language 2.213 9/5/2002

****	Support Cygwin (Windows) installations.  [Richard Dje]

* Verilog::Language 2.212 8/30/2002

***	Fix pin concatenations to not create false pins. [Kenneth Jiang]
	Concatenations are now just ignored; there is still no way to track
	pin interconnects where different bus bits end up interconnected
	differently.

* Verilog::Language 2.211 8/19/2002

***	If Verilog::Getopt list accessors are passed a reference,
	set the entire list to the reference, rather then adding a element.

* Verilog::Language 2.210 8/8/2002

****	Cleanups to support GNU Bison 1.35

****	Minor changes for SystemC support  

* Verilog::Language 2.200 5/3/2002

***	Many fixes to vrename --crypt, including fixing `timescale,
	comments, and replacement of strings.  [Greg Davis]

****	Fixed vpm $asserts dropping extra newlines. [Greg Waters]

****	Fixed `define substitution bug.

* Verilog::Language 2.100 3/11/2002 

**	Installation now requires GCC/G++ and Flex.

**	Added Verilog::Preproc, a Verilog 2001 Preprocessor.
	Verilog::Netlist now uses this preprocessor by default.

****	Fixed bug with vrename --crypt not working.  [Greg Davis]

****	Fixed bug with vrename and \ quoted signals.  [Greg Davis]

* Verilog::Language 2.010 11/16/2001

***	Added netlist interconnectivity checks.

* Verilog::Language 2.000 9/17/2001

**	Added the Verilog::Netlist package.
	This allows for simple scripts to extract pins, module
	hierarchy, etc from interconnected Verilog files.

***	Added Parser reset() method for clearing parse states
	for new files.  [Joe Panec]

* Verilog::Language 1.15 10/25/2001

**	Added $assert_req_ack for checking simple handshakes.

**	Added --nostop, and made --stop be the default.
	This adds a $stop to $warn and $error, which is easier
	for new users to understand as no pli.v is required.

* Verilog::Language 1.14 9/17/2001

***	Fixed bug when endmodule/endtask/endfunction have
	no trailing ;.  [Darren Jones]

***	Added Verilog 2001 keywords to Verilog::Language.

* Verilog::Language 1.13 5/17/2001

***	Added Verilog::Getopt::get_parameter() function.

***	Added Verilog::Getopt::file_abs() function.

***	Added missing keywords to Verilog::Language:
	deassign disable extern highz0 highz1 large medium pull0
	pull1 release scalared small strong0 strong1 weak0 weak1

* Verilog::Language 1.12 5/15/2001

**	Added new Verilog::Getopt, for standard option parsing.

* Verilog::Language 1.11 3/31/2001

***	Fixed \net### hang in Parser.  [Mark Lakata]

* Verilog::Language 1.10 3/15/2001

***	Fixed line number being incorrect in Parser.  [Alan Heinold]

* Verilog::Language 1.9 2/13/2001

**	Added Verilog::Language::is_compdirect.  [Darren Jones]

* Verilog::Language 1.7 11/02/2000

**	Added parametric module support to Parser.pm.  [Darren Jones]

****	Fixed bug where // comments with no following text broke.
	[Darren Jones]

* Verilog::Language 1.6 9/07/2000

**	Added the vpm preprocessor

****	Fixed bug where missing end-quote would hang Verilog::Parser

* Verilog::Language 1.5 5/22/2000

**	Allowed non-numerics in bus subscripts
	[Alan.Heinold@East.Sun.COM]

***	Fixed bug where lines with just a newline would boggle the linecount.

* Verilog::Language 1.4 1/21/2000

****	test.pl added

----------------------------------------------------------------------
$Id: Changes 46100 2007-10-18 13:21:22Z wsnyder $
DESCRIPTION: Documentation on change history for this package
----------------------------------------------------------------------

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