makepp_incompatibilities -- Incompatibilities between makepp and GNU make
Makepp was designed to be as close as possible to GNU make. However, because of the difference in philosophy (see makepp_build_algorithm), some of GNU make's features cannot be supported. Others have not been implemented because I haven't had time. Also, in order to emulate GNU make's behavior precisely, you may in some cases have to add additional command line options to the makepp command line, as noted below. Most of the differences from GNU make are quite technical and only rarely cause problems.
Makepp will give warning messages for many things which the traditional unix make accepts without flinching. This is because there are better ways to do them with makepp. If these warnings annoy you, you can turn them off with the
--nowarn command line option.
VPATHvariable is currently ignored.
vpathstatements are unsupported and will cause errors. Use repositories (see makepp_repositories) instead.
Pattern rules only match files in the directory (or if you include the
--percent-subdirsoption, in its subdirectories). This means that a rule like this:
%.o: %.c $(CC) $(CFLAGS) -c $(input) -o $(output)
will not be applied to files like
A pattern rule present later in a makefile overrides one that is present earlier. This is backwards from GNU make.
Default rules (pattern rules with no pattern dependencies) are not supported.
The set of builtin implicit rules (see makepp_builtin) is somewhat different from those for GNU make, though the variable names are largely compatible. The builtin rules should successfully compile C/C++/Fortran programs, and in fact may be able to guess the proper libraries in some cases too. Support for Modula-2 and RatFor and other rare languages is deliberately not present, because I kept running into problems with GNU make's rules when I accidently reused the extensions for those languages.
Archive members are not supported, and neither are the associated automatic variables
Leading and trailing whitespace in variable assignments is ignored (even if the whitespace is followed by a comment). For more details on whitespace handling incompatibilities, see "Whitespace in variables" in makepp_variables.
Whitespace in variable names is not supported.
Double colon rules are not currently supported; they are treated as single colon rules. Because of the way makepp is implemented, they will probably never be supported.
Makepp does not attempt to rebuild files included with the
includestatement unless the makefile contains a rule for building them before the include statement is seen. (It will attempt to rebuild the makefile itself, however.) This is normally used for handling include file dependencies, and is not as useful with makepp since you don't need to do that anyway.
SHELLvariable is currently ignored. makepp always uses
Dependencies of anything on the Makefile still work, but are usually unnecessary. This is usually used to force a rebuild when compilation options change. makepp knows when build commands have changed without anything special in the makefile; it stores this on a file-by-file basis. If you change the makefile, it knows exactly which files need recompilation.
$?is equivalent to
$+. See the the description of
$?for the reasons.
Intermediate files are not deleted. (Because makepp insists on having all of the file dates be the same as they were on the last build, intermediate files must all be present or else rebuilds will occur.) There is no special status accorded to intermediate files. This means that the special targets
The only special target that is supported is
.PHONY. The remaining are simply ingored.
Specifically, GNU make has the following special targets:
.SUFFIXESexcept for the special case of
.SUFFIXESwith no dependencies, like this:
which tells it not to load any of its default rules.
- .INTERMEDIATE, .SECONDARY, .PRECIOUS
No special status is accorded to intermediate files and so these targets are not meaningful.
This target is ignored. If you want to ignore errors, put the word
ignore_error(or a minus sign) in front of the command whose exit status is to be ignored.
This target is ignored. If you want commands not to echo, put the word
@character) in front of the command which is not supposed to be echoed.
These targets are not supported and are simply ignored.
Several GNU make functions are not currently supported. These are
$(wildcard )function matches not only files which exist, but also files which do not yet exist, but which have a rule which makepp has seen at the time the
$(wildcard )function is evaluated.
overridestatement is not supported.
-includewill not attempt to make the include file if it doesn't exist. Also, if the file exists but is out of date with respect to its dependencies, it will not be remade; it is not considered an implicit target.
This is usually used for files containing dependency information, and since makepp is able to compute a lot of this without depending on additional tools,
-includeis not as important as it used to be.
The makefile itself is ordinarily considered an implicit target. It will be rebuilt and reread if any of its dependencies have changed since the last time makepp rebuilt it.
"Canned command sequences" (strings defined with the
definestatement) are not supported.
Makepp does not support the following environment variables (it does not set them up, and it just ignores them):
Target-specific variables do not propagate their value to prerequistites of a rule. For example, with GNU make, you can do the following (taken from the GNU make info pages):
prog : CFLAGS = -g prog : prog.o foo.o bar.o
and each of the
.ofiles that will be compiled with
-g. This will <b>not</b> work with makepp. The reason is that it can lead to inconsistent builds. Consider the following makefile:
all: prog1 prog2 .PHONY: all CFLAGS = -O2 prog1: prog1.o a.o b.o $(CC) $(CFLAGS) $^ -o $@ prog2: CFLAGS = -g prog2: prog2.o a.o b.o $(CC) $^ -o $@ %.o: %.c $(CC) $< $(CFLAGS) -c -o $@
Now with the above makefile, suppose the user types
make all. What compilation option will
b.obe compiled with? There are contradictory specifications for
prog2. The file
a.omay only be compiled once on each invocation of makepp, so it cannot be compiled both ways. The result is an incorrect build of at least one of the programs. For this reason, makepp does not propagate target-specific variables to prerequisites of a rule.
% in a pattern rule does not match directories. Thus
%.c matches only
.c files in the current directory. If you want it to match files in subdirectories too, then add the
--percent-subdirs option to the command line. You can also enable this in your makefile by the assignment
By default, makepp will attempt to rebuild all targets if any of the dependencies have changed since the last build, or if the command has changed (see makepp_signatures for details). This is normally what you want. Sometimes, however, you don't want the target to be rebuilt if it has been modified apart from the control of makepp (e.g., by editing it, or by running a program manually to make the file). You can force makepp to use the traditional make algorithm, which only rebuilds if any of the targets are newer than the dependencies, by adding the option
-m target_newer to the command line.
As a special exception, any targets which are built while rebuilding the makefile are automatically checked using the
target_newer method in order to avoid problems with configure procedures.
Recursive invocations of make are often considered to be an unsafe practice (see "Better system for hierarchical builds" in makepp for details), but they are extremely common in existing makefiles. Makepp supports recursive make for backward compatibility; for new makefiles, it is much better to use the
load_makefile statement, or makepp's implicit makefile loading mechanism.
In order to be able to use repositories for variant builds, and to help make recursive invocations of make safter, makepp normally does not actually invoke itself recursively even if you tell it to. Instead, a subprocess communicates with the parent process, and the actual build is done by the parent process.
This works in most cases, but there are a few incompatibilities. (All of these incompatibilities are removed by adding the
--traditional-recursive-make option to the command line.)
You may not invoke several makefiles from the same directory, e.g., the following will not work:
target: dependencies $(MAKE) -f other_makefile targets
However, this will work:
target: dependencies cd subdir && $(MAKE) -f other_makefile targets
Changes in environment variables are not passed to the recursive make process; the environment of the parent is used instead.
MAKEFLAGSvariable is not set up, and altering it has no effect.
This may seem like a long list of restrictions, but many makefiles obey them. For example, as far as I know, all makefiles produced by
automake follow these restrictions.
All of these restrictions go away if you add the
--traditional-recursive-make option to the command line, but that has the following undesirable side effects:
Recursive makes do not execute in parallel, even if the parent does.
Recursive make processes do not know anything about repositories.
Each recursive make process produces its own log file, in the directory it is invoked in, instead of producing one log file for the entire build.
Even with the
--traditional-recursive-make option, the environment variables
MFLAGS not set up, and are ignored, so makefiles that depend on those will not work.
Rc-style substitution is the default way makepp performs variable substitution into text strings because it very rarely breaks legacy makefiles and is often useful in new makefiles. However, it does introduce occasional incompatibilities in the substitution of variables not surrounded by spaces. For example,
INCLUDE_PREFIX := -I/some/include/dir -I INCLUDES := $(INCLUDE_PREFIX)/other/include/dir
-I/some/include/dir/other/include/dir -I/other/include/dir if rc-style substitution is enabled, whereas GNU make would set it to
There is also an incompatibility in the handling of whitespace in a variable:
null := T := -o $(null) # T contains -o followed by one space. OUTFILE = $(T)outfile
-ooutfile if rc-style substitution is enabled, whereas GNU make would set it to
Both of these incompatibilities are removed by the
--norc-substitution option. Note, however, that even with
--norc-substitution, makepp still treats whitespace incompatibly in some situations:
T := -o # Don't delete this comment.
GNU make sets
T to contain
-o followed by a space, whereas makepp strips out the trailing space anyway. If you want the trailing space, you must specify
--norc-substitution and also set
T using the technique involving a dummy variable such as
null, as shown above.
At present, you may not combine single character options into a single word. E.g., you may not say
makepp -ejk 2 instead of
makepp -e -j 2 -k.
Makepp supports a few of make's more useful command line options. The following, however, are not supported, and are ignored after a warning message is printed:
- -d or --debug
- -l or --load-average or --max-load
-moption has to do with signature method selection, whereas GNU make ignores -m.
- -n or --just-print or --dry-run or --recon
- -o or --old-file or --assume-old
- -p or --print-data-base
- -q or --question
-qoption suppresses makepp's chatty informational messages, which is different from -q in GNU make.
- -r or --no-builtin-rules
- -R or --no-builtin-variables
-Roption actually does something completely different.
- -S --no-keep-going or --stop
- -t or --touch
- -w or --print-directory
- -W or --what-if or --new-file or --assume-new
Some of these can be easily supported if anyone cares.