NAME

Verilog::VCD::Writer - VCD waveform File creation module.

VERSION

version 0.001

SYNOPSIS

        use Verilog::VCD::Writer;

        my $writer=Verilog::VCD::Writer->new(timescale=>'1 ns',vcdfile=>"test.vcd");
        $writer->addComment("Author:Vijayvithal");

        my $top=$writer->addModule("top"); # Create toplevel module
        my $TX=$writer->addSignal("TX",7,0); #Add Signals to top
        my $RX=$writer->addSignal("RX",7,0);

        my $dut=$top->addModule("DUT");  Create SubModule
        $dut->dupSignal($TX,"TX",7,0); #Duplicate signals from Top in submodule
        $dut->dupSignal($RX,"RX",7,0);
        
        $writer->writeHeaders(); # Output the VCD Header.
        $writer->setTime(0); # Time 0
        $writer->addValue($TX,0); # Record Transition
        $writer->addValue($RX,0);
        $writer->setTime(5); # Time 1ns
        $writer->addValue($TX,1);
        $writer->addValue($RX,0);

METHODS

addComment(comment)

Adds a comment to the VCD file header. This method should be called before writeHeaders();

flush()

Flushes the output buffer.

DESCRIPTION This module originated out of my need to view the <Time,Voltage> CSV dump from the scope using GTKWave.

This module provides an interface for creating a VCD (Value change Dump) file.

new (timescale=>'1ps',vcdfile=>'test.vcd',date=>DateTime->now());

The constructor takes the following options

• timescale: default is '1ps'

• vcdfile: default is STDOUT, if a filename is given the VCD output will be written to it.

• Date: a DateTime object, default is current date.

writeHeaders()

This method should be called after all the modules and signals are declared. This method outputs the header of the VCD file

addModule(ModuleName)

This method takes the module name as an input string and returns the corresponding Verilog::VCD::Writer::Module object.

setTime(time)

This module takes the time information as an integer value and writes it out to the VCD file.

addValue(Signal,Value)

This method takes two parameters, an Object of the type Verilog::VCD::Writer::Signal and the decimal value of the signal at the current time. This module prints the <Signal,Value> information as a formatted line to the VCD file

AUTHOR

Vijayvithal Jahagirdar<jvs@cpan.org>

COPYRIGHT AND LICENSE

This software is copyright (c) 2017 by Vijayvithal.

This is free software; you can redistribute it and/or modify it under the same terms as the Perl 5 programming language system itself.