Verilog::VCD::Writer::Module - Module abstraction layer for Verilog::VCD::Writer
version 0.001
This method takes 3 parameters and returns a newly created Verilog::VCD::Writer::Signal Object.
Parameters are
name: Module name. Required. bitmax: The upper index of the bitrange e.g. for byte[7:0] bitmax is 7 bitmin: The lower index of the bitrange e.g. for byte[7:0] bitmin is 0
bitmax and bitmin are not required for a single bit signal.
Adds a signal to the current module which is an exact duplicate of a signal elsewhere.
The first parameter is a Verilog::VCD::Writer::Signal object, the rest are the same as the addSignal method.
Adds a submodule/function/task etc under the current module.
This method takes two parameter
name: Name of the module that will be added
type: a string which is either module,function or task
returns a newly created object of the type Verilog::VCD::Writer::Module
Vijayvithal Jahagirdar<jvs@cpan.org>
This software is copyright (c) 2017 by Vijayvithal.
This is free software; you can redistribute it and/or modify it under the same terms as the Perl 5 programming language system itself.
To install Verilog::VCD::Writer, copy and paste the appropriate command in to your terminal.
cpanm
cpanm Verilog::VCD::Writer
CPAN shell
perl -MCPAN -e shell install Verilog::VCD::Writer
For more information on module installation, please visit the detailed CPAN module installation guide.