NAME

App::Scheme79asm - assemble sexp to Verilog ROM for SIMPLE processor

SYNOPSIS

  use App::Scheme79asm;
  my $asm = App::Scheme79asm->new(type_bits => 3, addr_bits => 5);
  $asm->parse_and_print_verilog('(number 70)');

DESCRIPTION

SIMPLE is a LISP processor defined in the 1979 Design of LISP-Based Processors paper by Steele and Sussman.

The SIMPLE processor expects input in a particular tagged-pointer format. This module takes a string containing a sequence of S-expressions. Each S-expression is a list of one of three types:

(tag value), for example (symbol nil), represents a value to be put in memory (for example a number, or a symbol, or a variable reference).

(tag list), where list is of one of these three types, represents a tagged pointer. In this case, list is (recursively) laid out in memory as per these rules, and a pointer to that location (and tagged tag) is put somewhere in memory.

(tag list1 list2), where list1 and list2 are of one of these three types (not necessarily the same type). In this case, list1 and list2 are (recursively) laid out in memory such that list1 is at position X and list2 is at position X+1, and a pointer of type tag and value X is put somewhere in memory.

After this process the very last pointer placed in memory is moved to the special location 5 (which is where SIMPLE expects to find the expression to be evaluated).

In normal use a single S-expression will be supplied, representing an entire program.

The tag is either a number, a type, or a primitive. The available types are:

LIST

SYMBOL (syn. NUMBER)

VAR (syn. VARIABLE)

CLOSURE

PROC (syn. PROCEDURE)

IF (syn. COND, CONDITIONAL)

CALL

QUOTE (syn. QUOTED)

The available primitives are:

MORE

CAR

CDR

CONS

ATOM

PROGN

REVERSE-LIST

FUNCALL

The following methods are available:

App::Scheme79asm->new([key => value, key => value, ...])

Create a new assembler object. Takes a list of keys and values, here are the possible keys:

type_bits

address_bits

A word is made of a type and an address, with the type occupying the most significant type_bits (default 3) bits, and the address occupying the least significant address_bits (default 8) bits. Therefore the word size is type_bits + address_bits (default 13).

freeptr

A pointer to the last used byte in memory (default 6). The program will be laid out starting with location freeptr + 1.

memory

The initial contents of the memory. Note that locations 4, 5, 6 will be overwritten, as will every location larger than the value of freeptr.

comment

The initial comments for memory entries. $comment->[$i] is the comment for $memory->[$i].

symbols

The initial symbol map, as a hashref from symbol name to the index of that symbol. Defaults to {T => 2}.

nsymbols

The number to give to the "next" symbol (default 3, because T is defined to be 2).

$asm->parse($string)

Parse a sequence of S-expressions and lay it out in memory. Can be called multiple times to lay out multiple sequences of S-expressions one after another.

$asm->process($sexp)

Given an already-parsed sexp (meaning a Data::SExpression object), lay it out in memory. Can be called multiple times to lay out multiple sequences of S-expressions one after another.

$asm->finish

Move the last pointer to position 5, and put the free pointer at position 4. After all sequences of S-expressions have been given to parse, this method should be called.

$asm->print_binary16([$fh])

Print the length of the memory (as a big-endian 16-bit value), followed by the memory contents as a sequence of big-endian 16-bit values to the given filehandle (default STDOUT). Dies if addr_bits + type_bits is more than 16.

Big-endian 16-bit values can be decoded with unpack 'n', $value.

$asm->print_verilog([$fh])

Print a block of Verilog code assigning the memory contents to an array named mem to the given filehandle (default STDOUT).

$asm->parse_and_print_binary16($string[, $fh])

Convenience method that calls parse($string), finish, and then print_binary16($fh).

$asm->parse_and_print_verilog($string[, $fh])

Convenience method that calls parse($string), finish, and then print_verilog($fh).

SEE ALSO

http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf

AUTHOR

Marius Gavrilescu, <marius@ieval.ro>

COPYRIGHT AND LICENSE

Copyright (C) 2018 by Marius Gavrilescu

This library is free software; you can redistribute it and/or modify it under the same terms as Perl itself, either Perl version 5.24.3 or, at your option, any later version of Perl 5 you may have available.