Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist
use Verilog::Netlist; ... my $cell = $module->find_cell ('cellname'); print $cell->name;
Verilog::Netlist creates a cell for every instantiation in the current module.
The filename the cell was created in.
The line number the cell was created on.
Pointer to the module the cell is in.
The instantiation name of the cell.
List of pins connections for the cell.
Reference to the Verilog::Netlist::Module the cell instantiates. Only valid after the design is linked.
The module name the cell instantiates (under the cell).
Checks the cell for errors. Normally called by Verilog::Netlist::lint.
Creates a new Verilog::Netlist::Pin connection for this cell.
Prints debugging information for this cell.
Wilson Snyder <firstname.lastname@example.org>