Verilog::Netlist::Net - Net for a Verilog Module
use Verilog::Netlist; ... my $net = $module->find_net ('signalname'); print $net->name;
Verilog::Netlist creates a net for every sc_signal declaration in the current module.
Any array declaration for the net.
Any comment the user placed on the same line as the net.
The filename the net was created in.
The line number the net was created on.
Reference to the Verilog::Netlist::Module the net is in.
The name of the net.
The C++ type of the net.
Checks the net for errors. Normally called by Verilog::Netlist::lint.
Prints debugging information for this net.
Wilson Snyder <firstname.lastname@example.org>