NAME

Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist

SYNOPSIS

  use Verilog::Netlist;

  ...
  my $cell = $module->find_cell ('cellname');
  print $cell->name;

DESCRIPTION

Verilog::Netlist creates a cell for every instantiation in the current module.

ACCESSORS

$self->filename

The filename the cell was created in.

$self->lineno

The line number the cell was created on.

$self->module

Pointer to the module the cell is in.

$self->name

The instantiation name of the cell.

$self->pins

List of pins connections for the cell.

$self->submod

Reference to the Verilog::Netlist::Module the cell instantiates. Only valid after the design is linked.

$self->submodname

The module name the cell instantiates (under the cell).

MEMBER FUNCTIONS

$self->lint

Checks the cell for errors. Normally called by Verilog::Netlist::lint.

$self->new_pin

Creates a new Verilog::Netlist::Pin connection for this cell.

$self->dump

Prints debugging information for this cell.

SEE ALSO

Verilog::Netlist

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>