NAME
Verilog::Netlist::Net - Net for a Verilog Module
SYNOPSIS
use Verilog::Netlist;
...
my $net = $module->find_net ('signalname');
print $net->name;
DESCRIPTION
Verilog::Netlist creates a net for every sc_signal declaration in the current module.
ACCESSORS
- $self->array
-
Any array declaration for the net.
- $self->comment
-
Any comment the user placed on the same line as the net.
- $self->filename
-
The filename the net was created in.
- $self->lineno
-
The line number the net was created on.
- $self->module
-
Reference to the Verilog::Netlist::Module the net is in.
- $self->name
-
The name of the net.
- $self->type
-
The C++ type of the net.
MEMBER FUNCTIONS
- $self->lint
-
Checks the net for errors. Normally called by Verilog::Netlist::lint.
- $self->dump
-
Prints debugging information for this net.
SEE ALSO
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>