Verilog::Netlist::Pin - Pin on a Verilog Cell
use Verilog::Netlist; ... my $pin = $cell->find_pin ('pinname'); print $pin->name;
Verilog::Netlist creates a pin for every pin connection on a cell. A Pin connects a net in the current design to a port on the instantiated cell's module.
See also Verilog::Netlist::Subclass for additional accessors and methods.
Reference to the Verilog::Netlist::Cell the pin is under.
Reference to the Verilog::Netlist::Module the pin is in.
The name of the pin. May have extra characters to make vectors connect, generally portname is a more readable version. There may be multiple pins with the same portname, only one pin has a given name.
Reference to the Verilog::Netlist::Net the pin connects to. Only valid after a link.
Reference to the Verilog::Netlist the pin is in.
The net name the pin connects to.
The name of the port connected to.
Reference to the Verilog::Netlist::Port the pin connects to. Only valid after a link.
Checks the pin for errors. Normally called by Verilog::Netlist::lint.
Prints debugging information for this pin.
Verilog::Netlist::Subclass Verilog::Netlist
Wilson Snyder <wsnyder@wsnyder.org>
To install Verilog::Parse, copy and paste the appropriate command in to your terminal.
cpanm
cpanm Verilog::Parse
CPAN shell
perl -MCPAN -e shell install Verilog::Parse
For more information on module installation, please visit the detailed CPAN module installation guide.