NAME

Verilog::SigParser - Signal Parsing for Verilog language files

SYNOPSIS

  use Verilog::SigParser;

  my $parser = new Verilog::SigParser;
  $string = $parser->unreadback ();
  $line   = $parser->line ();
  $parser->parse_preproc_file ($pp);

DESCRIPTION

The Verilog::SigParser package builds upon the Verilog::Parse function to provide callbacks for when a signal is declared, a module instantiated, or a module defined. For a higher level interface to this package, see Verilog::Netlist.

The external interface to Verilog::SigParser is described in the Verilog::Parser module. You will probably want to use the preprocessing option of Verilog::Parser with this package.

In order to make the parser do anything interesting, you must make a subclass where you override one or more of the following methods as appropriate:

$self->module ( $keyword, $name )

This method is called when a module is defined.

$self->task ( $keyword, $name )

This method is called when a module is defined.

$self->function ( $keyword, $name )

This method is called when a function is defined.

$self->signal_decl ( $keyword, $signame, $vector, $mem )

This method is called when a signal is declared. The first argument, $keyword is ('input', 'output', etc), the second argument is the name of the signal. The third argument is the vector bits or "". The fourth argument is the memory bits or "".

$self->instant ( $module, $cell )

This method is called when a instantantiation is defined. The first parameter is the name of the module being instantiated, and the second parameter is the name of the cell.

SEE ALSO

Verilog::Parser, Verilog::Language, Verilog::Netlist, Verilog::Getopt,

BUGS

This is being distributed as a baseline for future contributions. Don\'t expect a lot, the Parser is still nieve, and there are many awkward cases that aren\'t covered.

DISTRIBUTION

The latest version is available from http://veripool.com/verilog-perl.

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>