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NAME

vpm - Preprocess verilog code

SYNOPSIS

vpm [ --help ] [ --date ] [ --quiet ] [ -y directories... ] [ files... ]

DESCRIPTION

Vpm will read the specified verilog files and preprocess them. The files are written to the directory named .vpm unless another name is given with -o. If a directory is passed, all files in that directory will be preprocessed.

ARGUMENTS

Standard VCS and GCC-like parameters are used to specify the files to be preprocessed:

    +libext+I<ext>+I<ext>...    Specify extensions to be processed
    -f I<file>          Parse parameters in file
    -v I<file>          Parse the library file (I<file>)
    -y I<dir>           Parse all files in the directory (I<dir>)
    -II<dir>            Parse all files in the directory (I<dir>)
    +incdir+I<dir>      Parse all files in the directory (I<dir>)

To prevent recursion and allow reuse of the input.vc being passed to the simulator, if the output directory is requested to be preprocessed, that directory is simply ignored.

--allfiles

Preprocess and write out files that do not have any macros that need expanding. By default, files that do not need processing are not written out.

This option may speed up simulator compile times; the file will always be found in the preprocessed directory, saving the compiler from having to search a large number of -v directories to find it.

--chiponly

Special standalone chip compile

--date

Check file dates versus the last run of VPM and don\'t process if the given source file has not changed.

--exclude

Exclude processing any files which begin with the specified prefix.

--help

Displays this message and program version and exits.

--quiet

Suppress messages about what files are being preprocessed.

--nostop

By default, $error and $warn insert a $stop statement. With --nostop, this is replaced by incrementing a variable, which may then be used to conditionally halt simulation.

--vericov

Special vericov enable/disables added.

--verilator

Special verilator translation enabled.

--o file

Use the given filename for output instead of the input name .vpm. If the name ends in a / it is used as a output directory with the default name.

FUNCTIONS

These verilog pseudo-pli calls are expanded:

$assert (case, "message", [vars...] )

Report a $error if the given case is FALSE. (Like assert() in C.)

$assert_amone (sig, [sig...], "message", [vars...] )

Report a $error if more then one signal is asserted, or any are X. (None asserted is ok.) The error message will include a binary display of the signal values.

$assert_info (case, "message", [vars...] )

Report a $info if the given case is FALSE. (Like assert() in C.)

$assert_onehot (sig, [sig...], "message", [vars...] )

Report a $error if other then one signal is asserted, or any are X. The error message will include a binary display of the signal values.

$assert_req_ack (req_sig, ack_sig, [data_sig,...] )

Check for a single cycle request pulse, followed by a single cycle acknowledgement pulse. Do not allow any of the data signals to change between the request and acknowledgement.

$check_ilevel (level )

Return true if the __message level is greater or equal to the given level, and that global messages are turned on.

$coverage (signal, [signal...] )

Add code to perform coverage analysis on all possible values of the given signals, or with $expand around a signal, the value of each bit independently.

$info (level, "message", [vars...] )

Report a informational message in standard form. End test if warning limit exceeded.

$error ("message", [vars...] )

Report a error message in standard form. End test if error limit exceeded.

$warn ("message", [vars...] )

Report a warning message in standard form.

SEE ALSO

Verilog::Parser, Verilog::Pli

DISTRIBUTION

The latest version is available from CPAN http://www.perl.org/CPAN/ as part of Verilog-Perl or http://veripool.com/verilog-perl.html.

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>, Duane Galbi <duane.galbi@conexant.com>