++ed by:
CXW

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5 non-PAUSE users.

Wilson Snyder

NAME

Verilog::Netlist - Verilog Netlist

SYNOPSIS

    use Verilog::Netlist;

    # Setup options so files can be found
    use Verilog::Getopt;
    my $opt = new Verilog::Getopt;
    $opt->parameter( "+incdir+verilog",
                     "-y","verilog",
                     );

    # Prepare netlist
    my $nl = new Verilog::Netlist (options => $opt,);
    foreach my $file ('testnetlist.sp') {
        $nl->read_file (filename=>$file);
    }
    # Read in any sub-modules
    $nl->link();
    $nl->lint();
    $nl->exit_if_error();

    foreach my $mod ($nl->top_modules_sorted) {
        show_hier ($mod, "  ", "", "");
    }

    sub show_hier {
        my $mod = shift;
        my $indent = shift;
        my $hier = shift;
        my $cellname = shift;
        if (!$cellname) {$hier = $mod->name;} #top modules get the design name
        else {$hier .= ".$cellname";} #append the cellname
        printf ("%-45s %s\n", $indent."Module ".$mod->name,$hier);
        foreach my $sig ($mod->ports_sorted) {
            printf ($indent."     %sput %s\n", $sig->direction, $sig->name);
        }
        foreach my $cell ($mod->cells_sorted) {
            printf ($indent. "    Cell %s\n", $cell->name);
            foreach my $pin ($cell->pins_sorted) {
                printf ($indent."     .%s(%s)\n", $pin->name, $pin->netname);
            }
            show_hier ($cell->submod, $indent."  ", $hier, $cell->name) if $cell->submod;
        }
    }

DESCRIPTION

Verilog::Netlist contains interconnect information about a whole design database.

The database is composed of files, which contain the text read from each file.

A file may contain modules, which are individual blocks that can be instantiated (designs, in Synopsys terminology.)

Modules have ports, which are the interconnection between nets in that module and the outside world. Modules also have nets, (aka signals), which interconnect the logic inside that module.

Modules can also instantiate other modules. The instantiation of a module is a Cell. Cells have pins that interconnect the referenced module's pin to a net in the module doing the instantiation.

Each of these types, files, modules, ports, nets, cells and pins have a class. For example Verilog::Netlist::Cell has the list of Verilog::Netlist::Pin (s) that interconnect that cell.

FUNCTIONS

See also Verilog::Netlist::Subclass for additional accessors and methods.

$netlist->lint

Error checks the entire netlist structure.

$netlist->link()

Resolves references between the different modules. If link_read=>1 is passed when netlist->new is called (it is by default), undefined modules will be searched for using the Verilog::Getopt package, passed by a reference in the creation of the netlist. To suppress errors in any missing references, set link_read_nonfatal=>1 also.

$netlist->new

Creates a new netlist structure. Pass optional parameters by name. The parameter "options" may contain a reference to a Verilog::Getopt module, to be used for locating files.

$netlist->dump

Prints debugging information for the entire netlist structure.

MODULE FUNCTIONS

$netlist->find_module($name)

Returns Verilog::Netlist::Module matching given name.

$netlist->modules

Returns list of Verilog::Netlist::Module.

$netlist->modules_sorted

Returns name sorted list of Verilog::Netlist::Module.

$netlist->new_module

Creates a new Verilog::Netlist::Module.

$netlist->top_modules_sorted

Returns name sorted list of Verilog::Netlist::Module, only for those modules which have no children and are not unused library cells.

FILE FUNCTIONS

$netlist->dependency_write(filename)

Writes a dependency file for make, listing all input and output files.

$netlist->defvalue_nowarn (define)

Return the value of the specified define or undef.

$netlist->dependency_in(filename)

Adds an additional input dependency for dependency_write.

$netlist->dependency_out(filename)

Adds an additional output dependency for dependency_write.

$netlist->files

Returns list of Verilog::Netlist::File.

$netlist->files_sorted

Returns a name sorted list of Verilog::Netlist::File.

$netlist->find_file($name)

Returns Verilog::Netlist::File matching given name.

$netlist->read_file( filename=>$name)

Reads the given Verilog file, and returns a Verilog::Netlist::File reference.

Generally called as $netlist->read_file. Pass a hash of parameters. Reads the filename=> parameter, parsing all instantiations, ports, and signals, and creating Verilog::Netlist::Module structures.

$netlist->read_libraries ()

Read any libraries specified in the options=> argument passed with the netlist constructor. Automatically invoked when netlist linking results in a module that wasn't found, and thus might be inside the libraries.

$netlist->remove_defines (string)

Expand any `defines in the string and return the results. Undefined defines will remain in the returned string.

$netlist->resolve_filename (string)

Convert a module name to a filename. Return undef if not found.

$self->verilog_text

Returns verilog code which represents the netlist.

BUGS

Cell instantiations without any arguments are not supported, a empty set of parenthesis are required. (Use "cell cell();", not "cell cell;".)

Order based pin interconnect is not supported, use name based connections.

DISTRIBUTION

The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.

Copyright 2000-2005 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

Verilog::Netlist::Cell, Verilog::Netlist::File, Verilog::Netlist::Module, Verilog::Netlist::Net, Verilog::Netlist::Pin, Verilog::Netlist::Port, Verilog::Netlist::Subclass