++ed by:
CXW

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5 non-PAUSE users.

Wilson Snyder

NAME

Verilog::Language - Verilog language utilities

SYNOPSIS

  use Verilog::Language;

  $result = Verilog::Language::is_keyword ("wire");  # true
  $result = Verilog::Language::is_compdirect ("`notundef");  # false
  $result = Verilog::Language::number_value ("4'b111");  # 8
  $result = Verilog::Language::number_bits  ("32'h1b");  # 32
  $result = Verilog::Language::number_signed ("1'sh1");  # 1
  @vec    = Verilog::Language::split_bus ("[31,5:4]"); # 31, 5, 4
  @vec    = Verilog::Language::split_bus_nocomma ("[31:29]"); # 31, 30, 29
  $result = Verilog::Language::strip_comments ("a/*b*/c");  # ac

DESCRIPTION

This package provides useful utilities for general use with the Verilog Language. General functions will be added as needed.

Verilog::Language::is_keyword ($symbol_string)

Return true if the given symbol string is a Verilog reserved keyword. Value indicates the language standard, 1995, 2001, or sv31 for SystemVerilog 3.1.

Verilog::Language::is_compdirect ($symbol_string)

Return true if the given symbol string is a Verilog compiler directive.

Verilog::Language::language_standard ($year)

Sets the language standard to indicate what are keywords. If undef, all standards apply. 1995 sets only Verilog 1995, 2001 sets Verilog 2001, and 'sv31' sets SystemVerilog 3.1.

Verilog::Language::number_bits ($number_string)

Return the number of bits in a value string, or undef if incorrectly formed, _or_ not specified.

Verilog::Language::number_signed ($number_string)

Return true if the Verilog value is signed, else undef.

Verilog::Language::number_value ($number_string)

Return the numeric value of a Verilog value, or undef if incorrectly formed. It ignores any signed Verilog attributes, but is is returned as a perl signed integer, so it may fail for over 31 bit values.

Verilog::Language::split_bus ($bus)

Return a list of expanded arrays. When passed a string like "foo[5:1:2,10:9]", it will return a array with ("foo[5]", "foo[3]", ...). It correctly handles connectivity expansion also, so that "x[1:0] = y[3:0]" will get intuitive results.

Verilog::Language::split_bus_nocomma ($bus)

As with split_bus, but faster. Only supports simple decimal colon separated array specifications, such as "foo[3:0]".

Verilog::Language::strip_comments ($text)

Return text with any // or /**/ comments stripped, correctly handing quoted strings. Newlines will be preserved in this process.

DISTRIBUTION

Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.

Copyright 2000-2006 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

Verilog::Parser, Verilog::ParseSig, Verilog::Getopt

And the http://www.veripool.com/verilog-mode.htmlVerilog-Mode package for Emacs.