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Wilson Snyder


vpm - Preprocess Verilog code assertions


vpm [ --help ] [ --date ] [ --quiet ] [ -y directories... ] [ files... ]


Vpm will read the specified verilog files and preprocess special PLI assertions. The files are written to the directory named .vpm unless another name is given with -o. If a directory is passed, all files in that directory will be preprocessed.


Standard VCS and GCC-like parameters are used to specify the files to be preprocessed:

    +libext+I<ext>+I<ext>...    Specify extensions to be processed
    -f I<file>          Parse parameters in file
    -v I<file>          Parse the library file (I<file>)
    -y I<dir>           Parse all files in the directory (I<dir>)
    -II<dir>            Parse all files in the directory (I<dir>)
    +incdir+I<dir>      Parse all files in the directory (I<dir>)

To prevent recursion and allow reuse of the input.vc being passed to the simulator, if the output directory is requested to be preprocessed, that directory is simply ignored.


Preprocess and write out files that do not have any macros that need expanding. By default, files that do not need processing are not written out.

This option may speed up simulator compile times; the file will always be found in the preprocessed directory, saving the compiler from having to search a large number of -v directories to find it.


Special standalone chip compile


Check file dates versus the last run of VPM and don't process if the given source file has not changed.


Exclude processing any files which begin with the specified prefix.


Displays this message and program version and exits.


Include `__message_minimum in the $uinfo test, so that by defining __message_minimum=1 some uinfos may be optimized away at compile time.


Delete all 'simple' PLI calls. PLI function calls inside parenthesis will not be changed, and thus may still need to be manually ifdef'ed out. Useful for reducing the amount of `ifdef's required to feed non-PLI competent synthesis programs.


Suppress messages about what files are being preprocessed.


By default, $error and $warn insert a $stop statement. With --nostop, this is replaced by incrementing a variable, which may then be used to conditionally halt simulation.

timeformat-units units

If specified, include Verilog $timeformat calls before all messages. Use the provided argument as the units. Units is in powers of 10, so -9 indicates to use nanoseconds.

timeformat-precision prec

When using --timeformat-units, use this as the precision value, the number of digits after the decimal point. Defaults to zero.


Special vericov enable/disables added.


Special verilator translation enabled.

--o file

Use the given filename for output instead of the input name .vpm. If the name ends in a / it is used as a output directory with the default name.


These verilog pseudo-pli calls are expanded:

$uassert (case, "message", [vars...] )

Report a $uerror if the given case is FALSE. (Like assert() in C.)

$uassert_amone (sig, [sig...], "message", [vars...] )

Report a $uerror if more then one signal is asserted, or any are X. (None asserted is ok.) The error message will include a binary display of the signal values.

$uassert_info (case, "message", [vars...] )

Report a $uinfo if the given case is FALSE. (Like assert() in C.)

$uassert_onehot (sig, [sig...], "message", [vars...] )

Report a $uerror if other then one signal is asserted, or any are X. The error message will include a binary display of the signal values.

$uassert_req_ack (req_sig, ack_sig, [data_sig,...] )

Check for a single cycle request pulse, followed by a single cycle acknowledgment pulse. Do not allow any of the data signals to change between the request and acknowledgement.

$ucheck_ilevel (level )

Return true if the __message level is greater or equal to the given level, and that global messages are turned on.

$ucoverage (signal, [signal...] )

Add code to perform coverage analysis on all possible values of the given signals, or with $uexpand around a signal, the value of each bit independently.

$uinfo (level, "message", [vars...] )

Report a informational message in standard form. End test if warning limit exceeded.

$uerror ("message", [vars...] )

Report a error message in standard form. End test if error limit exceeded.

$uwarn ("message", [vars...] )

Report a warning message in standard form.


Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.

Copyright 2000-2006 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.


Wilson Snyder <wsnyder@wsnyder.org>, Duane Galbi <duane.galbi@conexant.com>


Verilog::Parser, Verilog::Pli