Verilog::Netlist::Net - Net for a Verilog Module
use Verilog::Netlist; ... my $net = $module->find_net ('signalname'); print $net->name;
A Verilog::Netlist::Net object is created by Verilog::Netlist::Module for every signal and input/output declaration, and parameter in the current module.
See also Verilog::Netlist::Subclass for additional accessors and methods.
Any array (vector) declaration for the net. This is for multidimensional signals, for the width of a signal, use msb/lsb/width.
Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.
Reference to the Verilog::Netlist::Module the net is in.
The least significant bit number of the net.
The most significant bit number of the net.
The name of the net.
The C++ or declaration type of the net. For example "wire" or "parameter".
The width of the net in bits.
Checks the net for errors. Normally called by Verilog::Netlist::lint.
Prints debugging information for this net.
Prints debugging information for this net, and all pins driving the net.
Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.
Copyright 2000-2008 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.
Wilson Snyder <wsnyder@wsnyder.org>
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist
To install Verilog::Getopt, copy and paste the appropriate command in to your terminal.
cpanm
cpanm Verilog::Getopt
CPAN shell
perl -MCPAN -e shell install Verilog::Getopt
For more information on module installation, please visit the detailed CPAN module installation guide.