vhier - Return all files in a verilog hierarchy using Verilog::Netlist
vhier --help vhier [verilog_options] [-o filename] [verilog_files.v...]
Vhier reads the Verilog files passed on the command line and outputs a tree of all of the filenames, modules, and cells referenced by that file.
The following arguments are compatible with GCC, VCS and most Verilog programs.
Defines the given preprocessor symbol.
Read the specified file, and act as if all text inside it was specified as command line parameters.
Add the directory to the list of directories that should be searched for include directories or libraries.
Specify the extensions that should be used for finding modules. If for example module x is referenced, look in x.ext.
Displays this message and program version and exits.
Use the given filename for output instead of stdout.
Show the module name of all cells in top-down order.
Show all input filenames. Copying all of these files should result in only those files needed to represent the entire design.
Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop keyword).
Show all module filenames in top-down order. Child modules will always appear as low as possible, so that reversing the list will allow bottom-up processing of modules. Unlike input-files, header files are not included.
Show all module names.
Do not complain about references to missing modules.
With --nomissing, show all modules that are not found.
Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.
Copyright 2005-2008 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.
Wilson Snyder <wsnyder@wsnyder.org>
Verilog-Perl, Verilog::Getopt, Verilog::Preproc, Verilog::Netlist
To install Verilog::Getopt, copy and paste the appropriate command in to your terminal.
cpanm
cpanm Verilog::Getopt
CPAN shell
perl -MCPAN -e shell install Verilog::Getopt
For more information on module installation, please visit the detailed CPAN module installation guide.