NAME

Verilog::SigParser - Signal Parsing for Verilog language files

SYNOPSIS

  use Verilog::Preproc;
  use Verilog::SigParser;

  my $pp = Verilog::Preproc->new(keep_comments=>0,);

  my $parser = new Verilog::SigParser;
  $parser->parse_preproc_file ($pp);
  # The below described callbacks are then invoked

DESCRIPTION

Verilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined.

See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application. For a higher level interface to this package, see Verilog::Netlist.

METHODS

The method interface to Verilog::SigParser is described in the Verilog::Parser module which this package inherits. You will probably want to use the preprocessing option of Verilog::Parser with this package.

CALLBACKS

In order to make the parser do anything interesting, you must make a subclass where you override one or more of the following methods as appropriate:

$self->attribute ( $text )

Scanned an attribute or meta-comment. The parser inspects the first word of each comment line (//key rest to end of line) or comment block (/*key rest */). It calls $self-attribute( meta_text ) if the first word has a true value in hash $self-metacomment>.

$self->endcell ( $token )

This method is called at the end of defining a cell. It is useful for writing clean up routines.

$self->endinterface ( $token )

This method is called at a endinterface keyword. It is useful for writing clean up routines.

$self->endtaskfunc ( $token )

This method is called at a endfunction or endtask keyword. It is useful for writing clean up routines.

$self->endmodule ( $token )

This method is called at a endmodule keyword. It is useful for writing clean up routines.

$self->funcsignal ( $keyword, $signame, $vector, $mem, $signed, $value )

This method is called when a signal/variable is declared inside a function. See signal_decl for more details.

$self->function ( $keyword, $name, $type )

This method is called when a function is defined. Type is the output size or typename, plus "signed", for example "", "[3:0]", "integer", or "signed [2:0]".

$self->instant ( $module, $cell, $range )

This method is called when a instantiation is defined. The first parameter is the name of the module being instantiated. The second parameter is the name of the cell, which may be "" for primitives. The third is the range if the cell was arrayed.

Prior to version 3.000, the name of the parameters were also included in this callback. This has been replaced with the parampin callback.

$self->interface ( $keyword, $name )

This method is called when an interface is defined.

$self->module ( $keyword, $name, ignored, $in_celldefine )

This method is called when a module is defined.

$self->parampin ( $name, $connection, $index )

This method is called when a parameter is connected to an instantiation, IE the "#(...)" syntax. It is also used for UDP delays (Three calls for "#(delay0,delay1,delay2)"), as the parser does not know if the instantiation is for an UDP versus a module.

$self->pin ( $name, $connection, $index )

This method is called when a pin on a instant is defined. If a pin name was not provided and the connection is by position, name will be '' or undef.

$self->port ( $name )

This method is called when a module port is defined.

$self->ppdefine ( $defvar, $definition )

This method is called when a preprocessor definition is encountered.

$self->signal_decl ( $keyword, $signame, $vector, $mem, $signed, $value )

This method is called when a signal or variable is declared. The first argument, $keyword is a direction ('input', 'output', 'inout'), or a type ('reg', 'trireg', 'integer', 'parameter'), the second argument is the name of the signal. The third argument is the vector bits or "". The fourth argument is the memory bits or "". The fifth argument is "signed" if it is signed. The sixth argument is the value it is assigned to for "parameter" or "wire".

Note this may be called twice for signals that are declared with both a direction and a type. (IE 'output reg' results in a call with 'output' and a call with 'reg'.)

$self->task ( $keyword, $name )

This method is called when a module is defined.

BUGS

This is being distributed as a baseline for future contributions. Don't expect a lot, the Parser is still naive, and there are many awkward cases that aren't covered.

Note the SigParser is focused on extracting signal information. It does NOT extract enough information to derive general interconnect; for example the contents of 'assign' statements are not parsed.

DISTRIBUTION

Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

Copyright 2000-2008 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.

AUTHORS

Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO

Verilog-Perl, Verilog::Parser, Verilog::Language, Verilog::Netlist, Verilog::Getopt