++ed by:

1 PAUSE user
5 non-PAUSE users.

Wilson Snyder


vhier - Return all files in a verilog hierarchy using Verilog::Netlist


  vhier --help
  vhier [verilog_options] [-o filename] [verilog_files.v...]


Vhier reads the Verilog files passed on the command line and outputs a tree of all of the filenames, modules, and cells referenced by that file.


The following arguments are compatible with GCC, VCS and most Verilog programs.

+define+var+value =item -Dvar=value

Defines the given preprocessor symbol.

-f file

Read the specified file, and act as if all text inside it was specified as command line parameters.

+incdir+dir =item -Idir

Add the directory to the list of directories that should be searched for include directories or libraries.


Specify the extensions that should be used for finding modules. If for example module x is referenced, look in x.ext.

-y dir

Add the directory to the list of directories that should be searched for include directories or libraries.



Displays this message and program version and exits.

--o file

Use the given filename for output instead of stdout.


Show the module name of all cells in top-down order.


Show all input filenames. Copying all of these files should result in only those files needed to represent the entire design.

--language <1364-1995|1364-2001|1364-2005|1800-2005>

Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop keyword).


Show resolved filenames passed on the command line. This will convert raw module and filenames without paths to include the library search path directory. Output filenames will be in the same order as passed on the command line. Unlike --input-files or --module-files, hierarchy is not traversed.


Show all module filenames in top-down order. Child modules will always appear as low as possible, so that reversing the list will allow bottom-up processing of modules. Unlike input-files, header files are not included.


Show all module names.


Do not complain about references to missing modules.


With --nomissing, show all modules that are not found.

--top-module module

Start the report at the specified module name, ignoring all modules that are not the one specified with --top-module or below, and report an error if the --top-module specified does not exist. Without this option vhier will report all modules, starting at the module(s) that have no children below them.

Note this option will not change the result of the --input-files list, as the files needed to parse any design are independent of which modules are used.


Displays program version and exits.


Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

Copyright 2005-2009 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.


Wilson Snyder <wsnyder@wsnyder.org>


Verilog-Perl, Verilog::Getopt, Verilog::Preproc, Verilog::Netlist