Verilog::Netlist::Defparam - Defparam assignment
use Verilog::Netlist; ... foreach my $cont ($module->statements) print $cont->name;
A Verilog::Netlist::Defparam object is created by Verilog::Netlist for every defparam in the current module.
See also Verilog::Netlist::Subclass for additional accessors and methods.
Keyword used to declare the assignment. Currently "defparam" is the only supported value.
Left hand side of the assignment.
Pointer to the module the cell is in.
Reference to the Verilog::Netlist the cell is under.
Right hand side of the assignment.
Prints debugging information for this cell.
Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.
Copyright 2000-2017 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
Wilson Snyder <wsnyder@wsnyder.org>
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist
To install Verilog::Std, copy and paste the appropriate command in to your terminal.
cpanm
cpanm Verilog::Std
CPAN shell
perl -MCPAN -e shell install Verilog::Std
For more information on module installation, please visit the detailed CPAN module installation guide.