Verilog::Netlist::PinSelection - Nets attached to a Verilog Cell's Pins
Verilog::Netlist::PinSelection objects are used by Verilog::Netlist::Pin to define ranges of nets attached to the respective pin of a cell.
Name of the respective net, or, if use_pinselects is disabled, the string representation of the whole pin value. In the case of a sized constant only the part following the ' is stored while the width is encoded in the msb and lsb fields.
Least significant bit of the underlying net within the selection.
Most significant bit of the underlying net within the selection.
Returns the common string representation of a vectored net, e.g. netA[15:8].
Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.
Copyright 2000-2019 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
Stefan Tauner <tauner@technikum-wien.at> Wilson Snyder <wsnyder@wsnyder.org>
# =head1 SEE ALSO
# Verilog-Perl, # Verilog::Netlist # Verilog::Netlist::Pin
To install Verilog::Std, copy and paste the appropriate command in to your terminal.
cpanm
cpanm Verilog::Std
CPAN shell
perl -MCPAN -e shell install Verilog::Std
For more information on module installation, please visit the detailed CPAN module installation guide.