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Documentation
- bisonpre - Bison wrapper with pre and post processing
- callbackgen - Create callback functions for Verilog-Perl internals
- toolhash - Generate and hash files to avoid installation of build tools
- Verilog-Perl - Overview of Verilog language packages for Perl
- vhier - Return all files in a verilog hierarchy using Verilog::Netlist
- vpassert - Preprocess Verilog code assertions
- vppreproc - Preprocess Verilog code using verilog-perl
- vrename - change signal names across many Verilog files
Modules
- Verilog::EditFiles - Split Verilog modules into separate files.
- Verilog::Getopt - Get Verilog command line options
- Verilog::Language - Verilog language utilities
- Verilog::Netlist - Verilog Netlist
- Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist
- Verilog::Netlist::ContAssign - ContAssign assignment
- Verilog::Netlist::Defparam - Defparam assignment
- Verilog::Netlist::File - File containing Verilog code
- Verilog::Netlist::Interface - Interface within a Verilog Netlist
- Verilog::Netlist::Logger - Error collection and reporting
- Verilog::Netlist::ModPort - ModPort within a Verilog Interface
- Verilog::Netlist::Module - Module within a Verilog Netlist
- Verilog::Netlist::Net - Net for a Verilog Module
- Verilog::Netlist::Pin - Pin on a Verilog Cell
- Verilog::Netlist::Port - Port for a Verilog Module
- Verilog::Netlist::Subclass - Common routines for all classes
- Verilog::Parser - Parse Verilog language files
- Verilog::SigParser - Signal Parsing for Verilog language files
- Verilog::Preproc - Preprocess Verilog files
- Verilog::Std - SystemVerilog Built-in std Package Definition
Provides
- Verilog::Netlist::File::Parser in Netlist/File.pm
