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CXW

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5 non-PAUSE users.

Author image Wilson Snyder

Documentation

Bison wrapper with pre and post processing
Create callback functions for Verilog-Perl internals
Generate and hash files to avoid installation of build tools
Return all files in a verilog hierarchy using Verilog::Netlist
Preprocess Verilog code assertions
Preprocess Verilog code using verilog-perl
change signal names across many Verilog files

Modules

Split Verilog modules into separate files.
Get Verilog command line options
Verilog language utilities
Verilog Netlist
Instantiated cell within a Verilog Netlist
ContAssign assignment
Defparam assignment
File containing Verilog code
Interface within a Verilog Netlist
Error collection and reporting
ModPort within a Verilog Interface
Module within a Verilog Netlist
Net for a Verilog Module
Pin on a Verilog Cell
Nets attached to a Verilog Cell's Pins
Port for a Verilog Module
Common routines for all classes
Parse Verilog language files
Signal Parsing for Verilog language files
Preprocess Verilog files
SystemVerilog Built-in std Package Definition

Provides

in Netlist/File.pm
std
in Std.pm