use ExtUtils::MakeMaker;
# See lib/ExtUtils/MakeMaker.pm for details of how to influence
# the contents of the Makefile that is written.
WriteMakefile(
    'NAME'		=> 'Verilog::CodeGen',
    'VERSION_FROM'	=> 'CodeGen.pm', # finds $VERSION
    'PREREQ_PM'		=> {}, # e.g., Module::Name => 1.1
    ($] >= 5.005 ?    ## Add these new keywords supported since 5.005
      (ABSTRACT=> 'Verilog Code Generator', # retrieve abstract from module
       AUTHOR     => 'Wim Vanderbauwhede <wim@motherearth.org>') : ()),
);