Verilog-Perl - Overview of Verilog language packages for Perl River stage zero No dependents

The Verilog-Perl distribution provides Perl parsing and utilities for the Verilog Language. This file provides an overview of the distribution, for specific details on each component, see that component's manpage. You may also want to try the AUTO fe...

WSNYDER/Verilog-Perl-3.452 - 13 Apr 2018 02:29:01 GMT - Search in distribution

Perlilog - Verilog environment and IP core handling in Perl River stage zero No dependents

The project is extensively documented in Perlilog's user guide, which can be downloaded at <>. In wide terms, Perlilog is a Perl environment for Verilog code manipulation. It supplies the Perl programmer with se...

BILLAUER/Perlilog-1.0 - 01 May 2016 12:12:30 GMT - Search in distribution

cpan2dist - The CPANPLUS distribution creator River stage two • 33 direct dependents • 36 total dependents

This script will create distributions of "CPAN" modules of the format you specify, including its prerequisites. These packages can then be installed using the corresponding package manager for the format. Note, you can also do this interactively from...

BINGOS/CPANPLUS-0.9176 - 06 Jun 2018 15:22:15 GMT - Search in distribution

makepp_scanning - How makepp finds include files and other hidden dependencies River stage zero No dependents

Makepp can determine additional dependencies or targets for certain commands that it knows something about. This is especially important for C/C++ compilation, where it is too error-prone to list manually all of the include files that a given source ...

PFEIFFER/makepp- - 09 Nov 2017 09:32:03 GMT - Search in distribution

Text::EP3 - The Extensible Perl PreProcessor River stage zero No dependents

EP3 is a Perl5 program that preprocesses STDIN or some set of input files and produces an output file. EP3 only works on input files and produces output files. It seems to me that if you want to preprocess arrays or somesuch, you should be using perl...

MYKL/Text-EP3-1.10 - 02 Mar 2006 13:26:47 GMT - Search in distribution

Verilog::VCD - Parse a Verilog VCD text file River stage zero No dependents

Verilog is a Hardware Description Language (HDL) used to model digital logic. While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. This module can be used to parse a VCD file so that further ana...

GSULLIVAN/Verilog-VCD-0.08 - 04 May 2018 14:48:07 GMT - Search in distribution

Dir::Project - Project Environment determination River stage zero No dependents

Dir::Project provides a way to locate a source-controlled directory (CVS, Subversion, Perforce, Git, etc) using only the current working directory (cd). This prevents users from having to set other environment variables when they switch between areas...

WSNYDER/Dir-Project-3.026 - 26 Apr 2017 15:44:06 GMT - Search in distribution

Syntax::Highlight::Universal - Syntax highlighting module based on the Colorer library River stage zero No dependents

Syntax::Highlight::Universal doesn't export any functions. You can call its methods either statically or through an object. The result will be the same but we will use the latter here as it is the more convenient of the two. Creating a new object my ...

PALANT/Syntax-Highlight-Universal-0.4 - 13 Mar 2005 18:32:47 GMT - Search in distribution

App::Scheme79asm - assemble sexp to Verilog ROM for SIMPLE processor River stage zero No dependents

SIMPLE is a LISP processor defined in the 1979 Design of LISP-Based Processors paper by Steele and Sussman. The SIMPLE processor expects input in a particular tagged-pointer format. This module takes a string containing a sequence of S-expressions. E...

MGV/App-Scheme79asm-1.000 - 11 May 2018 19:20:26 GMT - Search in distribution

Syntax::Kamelon::Syntaxes - List of available syntaxes River stage zero No dependents

HANJE/Syntax-Kamelon-0.19 - 19 Dec 2017 10:38:01 GMT - Search in distribution

WWW::Pastebin::PastebinCom::API - implementation of API River stage one • 1 direct dependent • 1 total dependent

This module is an implementation of the API (<>). The API allows creation of public, unlisted, and private pastes; deletion of private pastes; listing of trending pastes and private pastes; and retrieval of a paste...

ZOFFIX/WWW-Pastebin-PastebinCom-API-1.001004 - 26 Dec 2016 18:31:10 GMT - Search in distribution

Hardware::Vhdl::Automake::Tutorial River stage zero No dependents

MYKL/Hardware-Vhdl-Automake-1.00 - 26 Nov 2009 16:01:25 GMT - Search in distribution

Syntax::Highlight::Engine::Kate - a port to Perl of the syntax highlight engine of the Kate text editor. River stage two • 10 direct dependents • 15 total dependents

This module is now deprecated. It is superseded and replaced by Syntax::Kamelon. Best use Syntax::Kamelon for new projects. Syntax::Highlight::Engine::Kate is a port to Perl of the syntax highlight engine of the Kate text editor. The language XML fil...

MANWAR/Syntax-Highlight-Engine-Kate-0.14 - 13 Jan 2018 21:00:27 GMT - Search in distribution

Module::Build::Xilinx - Perl module to create, build, simulate and program a Xilinx FPGA development board using Xilinx ISE Webpack from the commandline by leveraging Xilinx ISE's Tcl interface. River stage zero No dependents

WHAT DOES THE MODULE DO ? Xilinx ISE Webpack allows for commandline project creation, management, build/compile, run, simulation and programming of the device as well. However, Xilinx ISE Webpack only supports Tcl scripts using their custom "xtclsh" ...

VIKAS/Module-Build-Xilinx-0.13 - 28 Jul 2014 19:17:51 GMT - Search in distribution

Statocles::Plugin::Highlight - Highlight code and configuration syntax River stage one • 1 direct dependent • 1 total dependent

This plugin adds the "highlight" helper function to all templates and content documents, allowing for syntax highlighting of source code and configuration blocks....

PREACTION/Statocles-0.093 - 30 Mar 2018 22:33:23 GMT - Search in distribution

Verilog::Readmem - Parse Verilog $readmemh or $readmemb text file River stage zero No dependents

The Verilog Hardware Description Language (HDL) provides a convenient way to load a memory during logic simulation. The "$readmemh()" and "$readmemb()" system tasks are used in the HDL source code to import the contents of a text file into a memory v...

GSULLIVAN/Verilog-Readmem-0.05 - 09 Jul 2015 14:26:47 GMT - Search in distribution

Text::EP3::Verilog - Verilog extension for the EP3 preprocessor. River stage zero No dependents

This module is an EP3 extension for the Verilog Hardware Description Language. The signal directive @signal key definition Take a list of signals and generate signal lists in the differing formats that Verilog uses. This is accomplished by formatting...

GSPIVEY/Text-EP3-Verilog-1.00 - 13 Mar 1998 20:00:12 GMT - Search in distribution

Verilog::CodeGen - Verilog code generator River stage zero No dependents

Provides an object-oriented environment to generate Verilog code for modules and testbenches. The Verilog::CodeGen module provides two functions, one to create a code template and another to create a Perl module which contains the device library. Thi...

WVDB/Verilog-CodeGen-0.9.4 - 09 May 2003 14:55:35 GMT - Search in distribution

lib/Text/Restructured/Directive/ River stage one • 1 direct dependent • 1 total dependent

NODINE/Text-Restructured-0.003045 - 08 Dec 2010 20:34:25 GMT - Search in distribution

Pod::Parser::Groffmom::Color - Color formatting for groff -mom. River stage zero No dependents

OVID/Pod-Parser-Groffmom-0.042 - 11 Nov 2009 11:46:17 GMT - Search in distribution

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