Verilog::Language - Verilog language utilities River stage zero No dependents

Verilog::Language provides general utilities for using the Verilog Language, such as parsing numbers or determining what keywords exist. General functions will be added as needed....

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

Verilog::Parser - Parse Verilog language files River stage zero No dependents

Verilog::Parser will tokenize a Verilog file when the parse() method is called and invoke various callback methods. This is useful for extracting information and editing files while retaining all context. For netlist like extractions, see Verilog::Ne...

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

Verilog::SigParser - Signal Parsing for Verilog language files River stage zero No dependents

Verilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined. See the "Which Package" section of Verilog::Language if you are unsure which parsing package to ...

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

Verilog::VCD - Parse a Verilog VCD text file River stage zero No dependents

Verilog is a Hardware Description Language (HDL) used to model digital logic. While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. This module can be used to parse a VCD file so that further ana...

GSULLIVAN/Verilog-VCD-0.08 - 04 May 2018 14:48:07 GMT

Verilog::Std - SystemVerilog Built-in std Package Definition River stage zero No dependents

Verilog::Std contains the built-in "std" package required by the SystemVerilog standard....

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

Verilog::Getopt - Get Verilog command line options River stage zero No dependents

Verilog::Getopt provides standardized handling of options similar to Verilog/VCS and cc/GCC....

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

Verilog::Readmem - Parse Verilog $readmemh or $readmemb text file River stage zero No dependents

The Verilog Hardware Description Language (HDL) provides a convenient way to load a memory during logic simulation. The "$readmemh()" and "$readmemb()" system tasks are used in the HDL source code to import the contents of a text file into a memory v...

GSULLIVAN/Verilog-Readmem-0.05 - 09 Jul 2015 14:26:47 GMT

Verilog::Preproc - Preprocess Verilog files River stage zero No dependents

Verilog::Preproc reads Verilog files, and preprocesses them according to the SystemVerilog 2009 (1800-2009) specification. Programs can be easily converted from reading a IO::File into reading preprocessed output from Verilog::Preproc. See the "Which...

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

Verilog::Netlist - Verilog Netlist River stage zero No dependents

Verilog::Netlist reads and holds interconnect information about a whole design database. See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application. A Verilog::Netlist is composed of file...

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

Text::EP3::Verilog - Verilog extension for the EP3 preprocessor. River stage zero No dependents

This module is an EP3 extension for the Verilog Hardware Description Language. The signal directive @signal key definition Take a list of signals and generate signal lists in the differing formats that Verilog uses. This is accomplished by formatting...

GSPIVEY/Text-EP3-Verilog-1.00 - 13 Mar 1998 20:00:12 GMT

Verilog::VCD::Writer - VCD waveform File creation module. River stage zero No dependents

This module originated out of my need to view the <Time,Voltage> CSV dump from the scope using GTKWave. This module provides an interface for creating a VCD (Value change Dump) file. Please see examples/serial.pl for a complete example new (timescale...

JVS/Verilog-VCD-Writer-0.004 - 13 Dec 2017 03:21:45 GMT

Hardware::Verilog::Parser - A complete grammar for parsing Verilog code using perl River stage zero No dependents

This module defines the complete grammar needed to parse any Verilog code. By overloading this grammar, it is possible to easily create perl scripts which run through Verilog code and perform specific functions. For example, a Hierarchy.pm uses Hardw...

GSLONDON/Hardware-Verilog-Parser-0.13 - 27 Apr 2000 13:18:31 GMT

Verilog::VCD::Writer::Module - Module abstraction layer for Verilog::VCD::Writer River stage zero No dependents

JVS/Verilog-VCD-Writer-0.004 - 13 Dec 2017 03:21:45 GMT

Verilog::VCD::Writer::Signal - Signal abstraction layer for Verilog::VCD::Writer River stage zero No dependents

This module is designed to be called from the Verilog::VCD::Writer::Module module....

JVS/Verilog-VCD-Writer-0.004 - 13 Dec 2017 03:21:45 GMT

Verilog::VCD::Writer::Symbol - Signal name to symbol mapper. Private class nothing to see here. River stage zero No dependents

JVS/Verilog-VCD-Writer-0.004 - 13 Dec 2017 03:21:45 GMT

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