Verilog::SigParser - Signal Parsing for Verilog language files River stage zero No dependents
6 ++

Verilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined. See the "Which Package" section of Verilog::Language if you are unsure which parsing package to ...

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

Verilog::Std - SystemVerilog Built-in std Package Definition River stage zero No dependents
6 ++

Verilog::Std contains the built-in "std" package required by the SystemVerilog standard....

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

Verilog::Parser - Parse Verilog language files River stage zero No dependents
6 ++

Verilog::Parser will tokenize a Verilog file when the parse() method is called and invoke various callback methods. This is useful for extracting information and editing files while retaining all context. For netlist like extractions, see Verilog::Ne...

WSNYDER/Verilog-Perl-3.468 - 12 Sep 2019 22:48:11 GMT

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