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PFEIFFER / makepp-121020-test / t / verilog.test 

            

              
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###     SPAR <http://www.cpan.org/scripts/>
###     23      644     1143572799      1208276444      Makeppfile
fake_simv: in.vc : parser vcs_compilation
        -true -f $<          # true inexistent on native Win
        &touch $@
in.vc:
        &echo 'in.v\n-y .\n-v in.vlib\n+libext+.v+' -fo $@
in.v:
        &echo "`include \"in.vh\"" -fo $@
        &echo "module in;" -o >>$@
        &echo "reg a;" -o >>$@
        &echo "submod inst1(a);" -o >>$@
        &echo "libmod inst2(a);" -o >>$@
        &echo "endmodule" -o >>$@
submod.v:
        &echo 'module submod(a);\ninput a;\nendmodule' -o $@
in.vlib:
        &echo 'module libmod(a);\ninput a;\nendmodule' -o $@
in.vh:
        &echo "`define IN 1" -fo $@
###     D       755     1141170787      1141170770      answers
###     6       644     1141170733      1141170733      answers/in.v
`include "in.vh"
module in;
reg a;
submod inst1(a);
libmod inst2(a);
endmodule
###     4       644     1141170733      1141170733      answers/in.vc
in.v
-y .
-v in.vlib
+libext+.v+
###     1       644     1141170733      1141170733      answers/in.vh
`define IN 1
###     3       644     1141170733      1141170733      answers/in.vlib
module libmod(a);
input a;
endmodule
###     3       644     1141170770      1141170770      answers/submod.v
module submod(a);
input a;
endmodule