Verilog::VCD::Writer::Signal - Signal abstraction layer for Verilog::VCD::Writer
version 0.004
use Verilog::VCD::Writer; use Verilog::VCD::Writer::Signal; # my $signal=Verilog::VCD::Signal( # name=>'signalName', # type=> 'wire' # bitmax=>7, # bitmin=>0)
This module is designed to be called from the Verilog::VCD::Writer::Module module.
Vijayvithal Jahagirdar<jvs@cpan.org>
This software is copyright (c) 2017 by Vijayvithal.
This is free software; you can redistribute it and/or modify it under the same terms as the Perl 5 programming language system itself.
To install Verilog::VCD::Writer, copy and paste the appropriate command in to your terminal.
cpanm
cpanm Verilog::VCD::Writer
CPAN shell
perl -MCPAN -e shell install Verilog::VCD::Writer
For more information on module installation, please visit the detailed CPAN module installation guide.