Verilog::Netlist::Module - Module within a Verilog Netlist
use Verilog::Netlist; ... my $module = $netlist->find_module('modname'); my $cell = $self->find_cell('name') my $port = $self->find_port('name') my $net = $self->find_net('name')
A Verilog::Netlist::Module object is created by Verilog::Netlist for every module in the design.
See also Verilog::Netlist::Subclass for additional accessors and methods.
Returns list of references to Verilog::Netlist::Cell in the module.
Returns list of name sorted references to Verilog::Netlist::Cell in the module.
Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.
Returns the port name associated with the given index.
Returns true if the module has no cells referencing it (is at the top of the hierarchy.)
The name of the module.
Reference to the Verilog::Netlist the module is under.
Returns list of references to Verilog::Netlist::Net in the module.
Returns list of name sorted references to Verilog::Netlist::Net in the module.
Returns list of name sorted references to Verilog::Netlist::Net and Verilog::Netlist::Port in the module.
Returns list of references to Verilog::Netlist::Port in the module.
Returns list of references to Verilog::Netlist::Port in the order the ports were declared in the module's port list.
Returns list of name sorted references to Verilog::Netlist::Port in the module.
Updates the AUTOs for the module.
Returns Verilog::Netlist::Cell matching given name.
Returns Verilog::Netlist::Port matching given name.
Returns Verilog::Netlist::Net matching given name.
Checks the module for errors.
Creates interconnections between this module and other modules.
Uses a rough algorithm (drop the extension) to convert a filename to the module that is expected to be inside it.
Creates a new Verilog::Netlist::Cell.
Creates a new Verilog::Netlist::Port.
Creates a new Verilog::Netlist::Net.
Prints debugging information for this module.
Returns verilog code which represents this module. Returned as an array that must be joined together to form the final text string.
Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.
Copyright 2000-2007 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.
Wilson Snyder <wsnyder@wsnyder.org>
Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist
To install Verilog::Parse, copy and paste the appropriate command in to your terminal.
cpanm
cpanm Verilog::Parse
CPAN shell
perl -MCPAN -e shell install Verilog::Parse
For more information on module installation, please visit the detailed CPAN module installation guide.