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CXW
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Author image Wilson Snyder

Documentation

Overview of Verilog language packages for Perl
Return all files in a verilog hierarchy using Verilog::Netlist
vpm
Preprocess Verilog code assertions
Preprocess Verilog code using verilog-perl
change signal names across many Verilog files

Modules

Get Verilog command line options
Verilog language utilities
Verilog Netlist
Instantiated cell within a Verilog Netlist
File containing Verilog code
Module within a Verilog Netlist
Net for a Verilog Module
Pin on a Verilog Cell
Port for a Verilog Module
Common routines for all classes
parse Verilog language files
Parse Verilog language files
Preprocess Verilog files
Signal Parsing for Verilog language files

Provides

in Netlist/File.pm