The London Perl and Raku Workshop takes place on 26th Oct 2024. If your company depends on Perl, please consider sponsoring and/or attending.
 / 
Hardware-Verilog-Parser-0.10
River stage zero No dependents

Changes for version 0.10

  • Precompiled parser now works. Parses test1.v in about 6 seconds. generate_precompiled_parser.pl can't seem to properly insert the "use Hardware::Verilog::StdLogic" line correctly though. Have to manually edit the PrecompiledParser.pm file to do it correctly.

Modules

Hardware::Verilog::Parser
A complete grammar for parsing Verilog code using perl

Provides

Hardware::Verilog::Hierarchy
in Hierarchy.pm
Hardware::Verilog::PrecompiledParser
in PrecompiledParser.pm
Hardware::Verilog::StdLogic
in StdLogic.pm
Parse::RecDescent::namespace000001
in PrecompiledParser.pm

Other files