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Verilog-VCD-0.06
River stage zero No dependents
2 ++

Changes for version 0.06

  • parse all keywords now
  • allow all keyword contents to be multi-line
  • allow whitespace in timescale
  • added tests to increase coverage
  • improved error handling for non-VCD files

Modules

Verilog::VCD
Parse a Verilog VCD text file

Examples

Other files