Changes for version v0.12 - 2026-01-29
- Added experimental support for open with ports
- Added ac/accumulator to list of known logicals
- Added synthetic directives {read,write}_character, and {read,write}_be{8,16}
Modules
module for interacting with SIRTX VM code
module for assembling SIRTX VM code
module for assembling SIRTX VM code
module for single SIRTX VM opcodes
module for interacting with SIRTX VM code
module for interacting with SIRTX VM code