NAME
Verilog::Language - Verilog language utilities
SYNOPSIS
use Verilog::Language;
$result = Verilog::Language::is_keyword ($symbol_string)
$result = Verilog::Language::is_compdirect ($symbol_string)
$result = Verilog::Language::number_value ($number_string)
$result = Verilog::Language::number_bits ($number_string)
@vec = Verilog::Language::split_bus ($bus)
DESCRIPTION
This package provides useful utilities for general use with the Verilog Language. General functions will be added as needed.
- Verilog::Language::is_keyword ($symbol_string)
-
Return true if the given symbol string is a Verilog reserved keyword.
EXAMPLE
print Verilog::Language::is_keyword ("module");
1
print Verilog::Language::is_keyword ("signalname");
undef
- Verilog::Language::is_compdirect ($symbol_string)
-
Return true if the given symbol string is a Verilog compiler directive.
EXAMPLE
print Verilog::Language::is_compdirect ("`include");
1
print Verilog::Language::is_compdirect ("`MYDEFINE");
undef
- Verilog::Language::number_value ($number_string)
-
Return the numeric value of a Verilog value, or undef if incorrectly formed. Since it is returned as a signed integer, it may fail for over 31 bit integers.
EXAMPLE
print Verilog::Language::number_value ("32'h13");
19
print Verilog::Language::number_value ("32'p2");
undef
- Verilog::Language::number_bits ($number_string)
-
Return the number of bits in a value string, or undef if incorrectly formed, _or_ not specified.
EXAMPLE
print Verilog::Language::number_bits ("32'h13");
32
- Verilog::Language::split_bus ($bus)
-
Return a list of expanded arrays. When passed a string like "foo[5:1:2,10:9]", it will return a array with ("foo[5]", "foo[3]", ...). It correctly handles connectivity expansion also, so that "x[1:0] = y[3:0]" will get intuitive results.
- Verilog::Language::split_bus_nocomma ($bus)
-
As with split_bus, but faster. Only supports simple decimal colon separated array specifications, such as "foo[3:0]".
DISTRIBUTION
The latest version is available from http://veripool.com/verilog-perl
.
SEE ALSO
Verilog::Parser
, Verilog::ParseSig
, Verilog::Getopt
,
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>
8 POD Errors
The following errors were encountered while parsing the POD:
- Around line 47:
You forgot a '=back' before '=head1'
- Around line 54:
'=item' outside of any '=over'
- Around line 58:
You forgot a '=back' before '=head1'
- Around line 65:
'=item' outside of any '=over'
- Around line 71:
You forgot a '=back' before '=head1'
- Around line 78:
'=item' outside of any '=over'
- Around line 83:
You forgot a '=back' before '=head1'
- Around line 88:
'=item' outside of any '=over'