NAME
Verilog::Netlist::Pin - Pin on a Verilog Cell
SYNOPSIS
use Verilog::Netlist;
...
my $pin = $cell->find_pin ('pinname');
print $pin->name;
DESCRIPTION
Verilog::Netlist creates a pin for every pin connection on a cell. A Pin connects a net in the current design to a port on the instantiated cell's module.
ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and methods.
- $self->cell
-
Reference to the Verilog::Netlist::Cell the pin is under.
- $self->delete
-
Delete the pin from the cell it's under.
- $self->module
-
Reference to the Verilog::Netlist::Module the pin is in.
- $self->name
-
The name of the pin. May have extra characters to make vectors connect, generally portname is a more readable version. There may be multiple pins with the same portname, only one pin has a given name.
- $self->net
-
Reference to the Verilog::Netlist::Net the pin connects to. Only valid after a link.
- $self->netlist
-
Reference to the Verilog::Netlist the pin is in.
- $self->netname
-
The net name the pin connects to.
- $self->portname
-
The name of the port connected to.
- $self->port
-
Reference to the Verilog::Netlist::Port the pin connects to. Only valid after a link.
MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and methods.
- $self->lint
-
Checks the pin for errors. Normally called by Verilog::Netlist::lint.
- $self->dump
-
Prints debugging information for this pin.
SEE ALSO
Verilog::Netlist::Subclass Verilog::Netlist
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>