Verilog::Netlist::Net - Net for a Verilog Module
my $net = $module->find_net ('signalname');
Verilog::Netlist creates a net for every sc_signal declaration in the current module.
See also Verilog::Netlist::Subclass for additional accessors and methods.
Any array (vector) declaration for the net. This is for multidimensional signals, for the width of a signal, use msb/lsb/width.
Any comment the user placed on the same line as the net.
Reference to the Verilog::Netlist::Module the net is in.
The least significant bit number of the net.
The most significant bit number of the net.
The name of the net.
The C++ type of the net.
The width of the net in bits.
Checks the net for errors. Normally called by Verilog::Netlist::lint.
Prints debugging information for this net.
Prints debugging information for this net, and all pins driving the net.
Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.
Copyright 2000-2006 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.
Wilson Snyder <firstname.lastname@example.org>
To install Verilog::Parse, copy and paste the appropriate command in to your terminal.
perl -MCPAN -e shell
For more information on module installation, please visit the detailed CPAN module installation guide.