NAME
Verilog::Netlist::Port - Port for a Verilog Module
SYNOPSIS
use Verilog::Netlist;
...
my $port = $module->find_port ('pinname');
print $port->name;
DESCRIPTION
A Verilog::Netlist::Port object is created by Verilog::Netlist::Module for every port connection in the module.
ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and methods.
- $self->array
-
Any array declaration for the port.
- $self->comment
-
Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.
- $self->direction
-
The direction of the port: "in", "out", or "inout".
- $self->module
-
Reference to the Verilog::Netlist::Module the port is in.
- $self->name
-
The name of the port.
- $self->net
-
Reference to the Verilog::Netlist::Net the port connects to. Only valid after the netlist is linked.
- $self->type
-
The C++ type of the port.
MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and methods.
DISTRIBUTION
Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.
Copyright 2000-2007 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>