NAME
vhier - Return all files in a verilog hierarchy using Verilog::Netlist
SYNOPSIS
vhier --help
vhier [verilog_options] [-o filename] [verilog_files.v...]
DESCRIPTION
Vhier reads the Verilog files passed on the command line and outputs a tree of all of the filenames, modules, and cells referenced by that file.
VERILOG ARGUMENTS
The following arguments are compatible with GCC, VCS and most Verilog programs.
- +define+var+value =item -Dvar=value
-
Defines the given preprocessor symbol.
- -f file
-
Read the specified file, and act as if all text inside it was specified as command line parameters.
- +incdir+dir =item -Idir
-
Add the directory to the list of directories that should be searched for include directories or libraries.
- +libext+ext+ext...
-
Specify the extensions that should be used for finding modules. If for example module x is referenced, look in x.ext.
- -y dir
-
Add the directory to the list of directories that should be searched for include directories or libraries.
VHIER ARGUMENTS
- --help
-
Displays this message and program version and exits.
- --o file
-
Use the given filename for output instead of stdout.
- --cells
-
Show the module name of all cells in top-down order.
- --input-files
-
Show all input filenames. Copying all of these files should result in only those files needed to represent the entire design.
- --language <1364-1995|1364-2001|1364-2005|1800-2005>
-
Set the language standard for the files. This determines which tokens are signals versus keywords, such as the ever-common "do" (data-out signal, versus a do-while loop keyword).
- --module-files
-
Show all module filenames in top-down order. Child modules will always appear as low as possible, so that reversing the list will allow bottom-up processing of modules. Unlike input-files, header files are not included.
- --modules
-
Show all module names.
- --nomissing
-
Do not complain about references to missing modules.
- --missing-modules
-
With --nomissing, show all modules that are not found.
DISTRIBUTION
Verilog-Perl is part of the http://www.veripool.com/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.com/verilog-perl.html.
Copyright 2005-2008 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>
SEE ALSO
Verilog-Perl, Verilog::Getopt, Verilog::Preproc, Verilog::Netlist