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06 Jun 2021 13:45:35 UTC
- Distribution: Verilog-Perl
- Module version: 3.478
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Bus factor: 1- 66.12% Coverage
- License: perl_5
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NAME
Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist
SYNOPSIS
use Verilog::Netlist; ... my $cell = $module->find_cell('cellname'); print $cell->name;
DESCRIPTION
A Verilog::Netlist::Cell object is created by Verilog::Netlist for every instantiation in the current module.
ACCESSORS
See also Verilog::Netlist::Subclass for additional accessors and methods.
- $self->comment
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Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.
- $self->delete
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Delete the cell from the module it's under.
- $self->gateprim
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True if the cell is a gate primitive instantiation (buf/cmos/etc), but not a UDP.
- $self->module
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Pointer to the module the cell is in.
- $self->name
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The instantiation name of the cell.
- $self->netlist
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Reference to the Verilog::Netlist the cell is under.
- $self->pins
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List of Verilog::Netlist::Pin connections for the cell.
- $self->pins_sorted
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List of name sorted Verilog::Netlist::Pin connections for the cell.
- $self->range
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The range for the cell (e.g. "[1:0]") or false (i.e. undef or "") if not ranged.
- $self->submod
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Reference to the Verilog::Netlist::Module the cell instantiates. Only valid after the design is linked.
- $self->submodname
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The module name the cell instantiates (under the cell).
MEMBER FUNCTIONS
See also Verilog::Netlist::Subclass for additional accessors and methods.
- $self->lint
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Checks the cell for errors. Normally called by Verilog::Netlist::lint.
- $self->new_pin
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Creates a new Verilog::Netlist::Pin connection for this cell.
- $self->pins_sorted
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Returns all Verilog::Netlist::Pin connections for this cell.
- $self->dump
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Prints debugging information for this cell.
DISTRIBUTION
Verilog-Perl is part of the https://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from https://www.veripool.org/verilog-perl.
Copyright 2000-2021 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
AUTHORS
Wilson Snyder <wsnyder@wsnyder.org>
SEE ALSO
Module Install Instructions
To install Verilog::Std, copy and paste the appropriate command in to your terminal.
cpanm Verilog::Std
perl -MCPAN -e shell install Verilog::Std
For more information on module installation, please visit the detailed CPAN module installation guide.